Fully depleted SOI devices are very good for low-voltage, low-power applications. Firstly,
the source and drain parasitic resistances are reduced, so, less useless charge has to be
pumped into these capacitances.
Then, the body factor ("n" in the formulae below) is smaller in FDSOI than in
bulk (in all regimes of operation):
This shows the threshold voltage required to reach a speed performance of 250 MHz
(constant speed) in bulk and SOI circuits. The Vth=Vdd/4 figure is given for comparison...
Now, the real stuff: although the reduction of load capacitances provides by the use of
SOI is only 15-20%, compared to bulk (see references below), the power consumption and the
supply voltage can be substantially reduced using SOI...
Analog circuits: the use of FDSOI helps here, too. Here is the Bode diagram of a
micropower SOI Operational Transconductance Amplifier (OTA). If you do this in bulk CMOS,
you cannot expect a gain higher than 75 dB. Note the excellent high-temperature
performances...
D. Flandre and J.P. Colinge, "Status and Trends of SOI", Invited paper at
ESSCIRC 1994 (Sept. 94), Proceedings of ESSCIRC, pp. 18-27
"SOI technology for low-power, low-voltage applications", MEAD and EPFL course on "low-power, low-voltage design", Santa Clara (USA) and Lausanne (Switzerland), 1995
B. Gentinne, J.P. Eggermont and J.P. Colinge, "Performances of SOI CMOS OTA combining ZTC and gain-boosting techniques", Electronics Letters, Vol. 32, No. 24, pp. 2092-2093, 1995
D. Flandre, "Silicon-on-insulator technology for high temperature metal oxide semiconductor devices and circuits", Materials Science & Engineering - B, 29 (1995), pp. 7-12.
D. Flandre, P. Jespers, "Charge-sheet modelling of MOS I-V fundamental nonlinearities in MOSFET-C continuous-time filters", Electronics Letters, 31 (1995), pp. 1419-1420.
"SOI technology for low-power, low-voltage applications", Short Course on SOI circuits, IEEE International SOI Conference, 1996
D. Flandre, L. Ferreira, P.G.A. Jespers, J.-P. Colinge, "Modelling and application of fully-depleted SOI MOSFETs for low-voltage low-power analogue CMOS circuits", Solid-State Electronics, 39 (1996), pp. 455-460.
B. Iniguez, L.F. Ferreira, B. Gentinne and D. Flandre, "A physically-based Cµ-continuous fully-depleted SOI MOSFET model for analog applications", IEEE Trans. on Electron Devices, 43 (1996), pp. 568-575.
J.P. Colinge, "Recent advances and trends in SOI CMOS technology", Proceedings of the 26th European Solid State Device Research Conference (ESSDERC), Ed. by. G. Baccarani and M. Rudan, Editions Frontičres, pp. 935-942, 1996
J.P. Eggermont, D. De Ceuster, D. Flandre, B. Gentinne, P.G.A. Jespers and J.P.
Colinge, "Design of SOI CMOS operational amplifiers for applications up to
300°C", IEEE J. Solid-State Circuits, vol. 31-2 (1996), pp. 179-186
D. Flandre, L.F. Ferreira, P.G.A. Jespers and J.P. Colinge, "Modelling and
application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS
circuits", Solid-State Electronics, Vol. 39-4, pp. 455-460, 1996
J.P. Colinge, "SOI technology", in "Low-power HF microelectronics: a unified approach", edited by G.A.S. Machado, IEE circuits and systems series 8, the Institution of Electrical Engineers, pp. 139-184, 1996.
F. Silveira, D. Flandre, P.G.A. Jespers, "A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a Silicon-on-Insulator micropower OTA", IEEE Journal of Solid-State Circuits, 31 (1996), pp. 1613-1619.
D. Flandre, A. Viviani, J.-P. Eggermont, P. Jespers, "Improved synthesis of regulated-cascode gain-boosting CMOS stage using symbolic analysis and gm/ID methodology", sollicited contribution to IEEE Journal of Solid-State Circuits (Special Issue on 22nd ESSCIRC conference), 32 (1997), pp. 1006-1012.
D. Flandre et al, "Fully-depleted SOI CMOS technology for low-voltage low-power
mixed digital/analog/microwave circuits", Analog Integrated Circuits and Signal
Processing, 21 (1999), pp. 213-228.
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